pmc: SQ_INST_LEVEL_VMEM SQ_INST_LEVEL_VMEM_ACCUM SQ_INSTS SQ_INSTS_BRANCH SQ_INSTS_GDS SQ_INSTS_LDS SQ_INSTS_LDS_ATOMIC SQ_INSTS_LDS_ATOMIC_BANDWIDTH TA_BUFFER_WRITE_WAVEFRONTS_sum TA_DATA_STALLED_BY_TC_CYCLES_sum TCP_TCC_NC_WRITE_REQ_sum TCP_TCC_READ_REQ_LATENCY_sum TCP_TCC_READ_REQ_sum TCP_TCC_RW_ATOMIC_REQ_sum TCC_EA0_RDREQ_DRAM_sum TCC_EA0_RDREQ_GMI_32B_sum TCC_EA0_RDREQ_GMI_CREDIT_STALL[0] TCC_EA0_RDREQ_GMI_CREDIT_STALL[100] TCC_EA0_RDREQ_GMI_CREDIT_STALL[101] TCC_EA0_RDREQ_GMI_CREDIT_STALL[102] TCC_EA0_RDREQ_GMI_CREDIT_STALL[103] TCC_EA0_RDREQ_GMI_CREDIT_STALL[104] TCC_EA0_RDREQ_GMI_CREDIT_STALL[105] TCC_EA0_RDREQ_GMI_CREDIT_STALL[106] TCC_EA0_RDREQ_GMI_CREDIT_STALL[107] TCC_EA0_RDREQ_GMI_CREDIT_STALL[108] TCC_EA0_RDREQ_GMI_CREDIT_STALL[109] TCC_EA0_RDREQ_GMI_CREDIT_STALL[10] TCC_EA0_RDREQ_GMI_CREDIT_STALL[110] TCC_EA0_RDREQ_GMI_CREDIT_STALL[111] TCC_EA0_RDREQ_GMI_CREDIT_STALL[112] TCC_EA0_RDREQ_GMI_CREDIT_STALL[113] TCC_EA0_RDREQ_GMI_CREDIT_STALL[114] TCC_EA0_RDREQ_GMI_CREDIT_STALL[115] TCC_EA0_RDREQ_GMI_CREDIT_STALL[116] TCC_EA0_RDREQ_GMI_CREDIT_STALL[117] TCC_EA0_RDREQ_GMI_CREDIT_STALL[118] TCC_EA0_RDREQ_GMI_CREDIT_STALL[119] TCC_EA0_RDREQ_GMI_CREDIT_STALL[11] TCC_EA0_RDREQ_GMI_CREDIT_STALL[120] TCC_EA0_RDREQ_GMI_CREDIT_STALL[121] TCC_EA0_RDREQ_GMI_CREDIT_STALL[122] TCC_EA0_RDREQ_GMI_CREDIT_STALL[123] TCC_EA0_RDREQ_GMI_CREDIT_STALL[124] TCC_EA0_RDREQ_GMI_CREDIT_STALL[125] TCC_EA0_RDREQ_GMI_CREDIT_STALL[126] TCC_EA0_RDREQ_GMI_CREDIT_STALL[127] TCC_EA0_RDREQ_GMI_CREDIT_STALL[12] TCC_EA0_RDREQ_GMI_CREDIT_STALL[13] TCC_EA0_RDREQ_GMI_CREDIT_STALL[14] TCC_EA0_RDREQ_GMI_CREDIT_STALL[15] TCC_EA0_RDREQ_GMI_CREDIT_STALL[16] TCC_EA0_RDREQ_GMI_CREDIT_STALL[17] TCC_EA0_RDREQ_GMI_CREDIT_STALL[18] TCC_EA0_RDREQ_GMI_CREDIT_STALL[19] TCC_EA0_RDREQ_GMI_CREDIT_STALL[1] TCC_EA0_RDREQ_GMI_CREDIT_STALL[20] TCC_EA0_RDREQ_GMI_CREDIT_STALL[21] TCC_EA0_RDREQ_GMI_CREDIT_STALL[22] TCC_EA0_RDREQ_GMI_CREDIT_STALL[23] TCC_EA0_RDREQ_GMI_CREDIT_STALL[24] TCC_EA0_RDREQ_GMI_CREDIT_STALL[25] TCC_EA0_RDREQ_GMI_CREDIT_STALL[26] TCC_EA0_RDREQ_GMI_CREDIT_STALL[27] TCC_EA0_RDREQ_GMI_CREDIT_STALL[28] TCC_EA0_RDREQ_GMI_CREDIT_STALL[29] TCC_EA0_RDREQ_GMI_CREDIT_STALL[2] TCC_EA0_RDREQ_GMI_CREDIT_STALL[30] TCC_EA0_RDREQ_GMI_CREDIT_STALL[31] TCC_EA0_RDREQ_GMI_CREDIT_STALL[32] TCC_EA0_RDREQ_GMI_CREDIT_STALL[33] TCC_EA0_RDREQ_GMI_CREDIT_STALL[34] TCC_EA0_RDREQ_GMI_CREDIT_STALL[35] TCC_EA0_RDREQ_GMI_CREDIT_STALL[36] TCC_EA0_RDREQ_GMI_CREDIT_STALL[37] TCC_EA0_RDREQ_GMI_CREDIT_STALL[38] TCC_EA0_RDREQ_GMI_CREDIT_STALL[39] TCC_EA0_RDREQ_GMI_CREDIT_STALL[3] TCC_EA0_RDREQ_GMI_CREDIT_STALL[40] TCC_EA0_RDREQ_GMI_CREDIT_STALL[41] TCC_EA0_RDREQ_GMI_CREDIT_STALL[42] TCC_EA0_RDREQ_GMI_CREDIT_STALL[43] TCC_EA0_RDREQ_GMI_CREDIT_STALL[44] TCC_EA0_RDREQ_GMI_CREDIT_STALL[45] TCC_EA0_RDREQ_GMI_CREDIT_STALL[46] TCC_EA0_RDREQ_GMI_CREDIT_STALL[47] TCC_EA0_RDREQ_GMI_CREDIT_STALL[48] TCC_EA0_RDREQ_GMI_CREDIT_STALL[49] TCC_EA0_RDREQ_GMI_CREDIT_STALL[4] TCC_EA0_RDREQ_GMI_CREDIT_STALL[50] TCC_EA0_RDREQ_GMI_CREDIT_STALL[51] TCC_EA0_RDREQ_GMI_CREDIT_STALL[52] TCC_EA0_RDREQ_GMI_CREDIT_STALL[53] TCC_EA0_RDREQ_GMI_CREDIT_STALL[54] TCC_EA0_RDREQ_GMI_CREDIT_STALL[55] TCC_EA0_RDREQ_GMI_CREDIT_STALL[56] TCC_EA0_RDREQ_GMI_CREDIT_STALL[57] TCC_EA0_RDREQ_GMI_CREDIT_STALL[58] TCC_EA0_RDREQ_GMI_CREDIT_STALL[59] TCC_EA0_RDREQ_GMI_CREDIT_STALL[5] TCC_EA0_RDREQ_GMI_CREDIT_STALL[60] TCC_EA0_RDREQ_GMI_CREDIT_STALL[61] TCC_EA0_RDREQ_GMI_CREDIT_STALL[62] TCC_EA0_RDREQ_GMI_CREDIT_STALL[63] TCC_EA0_RDREQ_GMI_CREDIT_STALL[64] TCC_EA0_RDREQ_GMI_CREDIT_STALL[65] TCC_EA0_RDREQ_GMI_CREDIT_STALL[66] TCC_EA0_RDREQ_GMI_CREDIT_STALL[67] TCC_EA0_RDREQ_GMI_CREDIT_STALL[68] TCC_EA0_RDREQ_GMI_CREDIT_STALL[69] TCC_EA0_RDREQ_GMI_CREDIT_STALL[6] TCC_EA0_RDREQ_GMI_CREDIT_STALL[70] TCC_EA0_RDREQ_GMI_CREDIT_STALL[71] TCC_EA0_RDREQ_GMI_CREDIT_STALL[72] TCC_EA0_RDREQ_GMI_CREDIT_STALL[73] TCC_EA0_RDREQ_GMI_CREDIT_STALL[74] TCC_EA0_RDREQ_GMI_CREDIT_STALL[75] TCC_EA0_RDREQ_GMI_CREDIT_STALL[76] TCC_EA0_RDREQ_GMI_CREDIT_STALL[77] TCC_EA0_RDREQ_GMI_CREDIT_STALL[78] TCC_EA0_RDREQ_GMI_CREDIT_STALL[79] TCC_EA0_RDREQ_GMI_CREDIT_STALL[7] TCC_EA0_RDREQ_GMI_CREDIT_STALL[80] TCC_EA0_RDREQ_GMI_CREDIT_STALL[81] TCC_EA0_RDREQ_GMI_CREDIT_STALL[82] TCC_EA0_RDREQ_GMI_CREDIT_STALL[83] TCC_EA0_RDREQ_GMI_CREDIT_STALL[84] TCC_EA0_RDREQ_GMI_CREDIT_STALL[85] TCC_EA0_RDREQ_GMI_CREDIT_STALL[86] TCC_EA0_RDREQ_GMI_CREDIT_STALL[87] TCC_EA0_RDREQ_GMI_CREDIT_STALL[88] TCC_EA0_RDREQ_GMI_CREDIT_STALL[89] TCC_EA0_RDREQ_GMI_CREDIT_STALL[8] TCC_EA0_RDREQ_GMI_CREDIT_STALL[90] TCC_EA0_RDREQ_GMI_CREDIT_STALL[91] TCC_EA0_RDREQ_GMI_CREDIT_STALL[92] TCC_EA0_RDREQ_GMI_CREDIT_STALL[93] TCC_EA0_RDREQ_GMI_CREDIT_STALL[94] TCC_EA0_RDREQ_GMI_CREDIT_STALL[95] TCC_EA0_RDREQ_GMI_CREDIT_STALL[96] TCC_EA0_RDREQ_GMI_CREDIT_STALL[97] TCC_EA0_RDREQ_GMI_CREDIT_STALL[98] TCC_EA0_RDREQ_GMI_CREDIT_STALL[99] TCC_EA0_RDREQ_GMI_CREDIT_STALL[9] TCC_EA0_RDREQ_GMI_CREDIT_STALL_sum CPC_ME1_BUSY_FOR_PACKET_DECODE CPC_ME1_DC0_SPI_BUSY SPI_RA_WAVE_SIMD_FULL_CSN SPI_RA_WVLIM_STALL_CSN SPI_SWC_CSC_WR SPI_VWC0_VDATA_VALID_WR SPI_VWC1_VDATA_VALID_WR

gpu:
range:
kernel:
